In the design of integrated circuits, a common design process is to build large blocks using a module generator or by hand. These blocks are then routed together at the top level of the integrated circuit. In hierarchical design methodologies, this process may be used at several different levels of hierarchy. Many designs allow for spaces between these blocks to allow for routing. Also, often the modules, or component pieces of the modules, do not fit together exactly and gaps are left between or within modules of the integrated circuit. These gaps or routing channels typically are unused except for the interconnect layers.
As integrated circuit processes progress to smaller and smaller transistor geometries, several problems manifest themselves. With smaller and faster transistors, routing delay due to the resistance and capacitance of the interconnect wiring becomes a larger and larger part of the total circuit delay. Often, for very long interconnect traces, it is necessary to buffer the signal for performance. As those skilled in the art realize, there is an ideal location for a single buffer, typically near the midpoint of the routing trace. Sometimes it is necessary to add several buffers distributed along the length of the route.
As gate oxide thickness shrinks with more advanced processing, the gates become very susceptible to damage during processing due to charge collecting on the interconnect layers attached to the gates. For example, a very small gate connected to a very large area of first level metal may be damaged during processing as charge builds up on the metal with no discharge path except through the gate oxide. This problem may also occur in circuits that have a connection to active area in addition to gate connections. If the connection to active area is very far away from the gate, and the connection uses upper levels of interconnect, charge may still build up on the lower levels of interconnect during fabrication, since the upper levels may not have been deposited yet to complete the connection to the active area. Due to this problem, designers must carefully construct their interconnect such that a discharge path for this charge is available at all stages in the process where charge collection may occur.
Further problems result from the ever increasing switching current per unit area as processes become faster and smaller. This switching current causes spikes, or dips, in the power supplies that may become quite severe in circuits where a large number of gates switch simultaneously. The spikes, or dips, in the power supplies, often called ground bounce when they occur on the ground node, may be sufficient to move the supply voltage beyond the threshold voltage of the field effect transistors (FETs) and cause functional failures. One mitigating design technique is the addition of bypass capacitors between the power supplies. This is difficult to accomplish on the integrated circuit, since capacitors take up large amounts of area, raising the cost of the circuit.
As integrated circuits become smaller and faster, the number of processing steps required for production tends to increase. This often requires a larger number of masks to fabricate the circuits. Also, as geometries shrink, the mask production becomes more difficult and hence more expensive. When an error is found in the design of an integrated circuit, the masks often must be completely rebuilt to correct the error. Since masks are expensive, designers work very hard to make their fixes in the fewest number of masks as possible. Also, since fabrication of integrated circuits takes a substantial amount of time, it is desirable to make the changes to the masks which are used at the latest possible step in the fabrication process so that fabrication Of the corrected circuit may begin with the existing masks simultaneously with the manufacture of the corrected masks. This reduction in the time required for error repairs is very valuable to the designers of the system that the integrated circuit will be used in.
One of the most common design errors is the creation of a signal that is too slow to meet the speed requirements of the circuit. Sometimes this error may be fixed by buffering the signal to speed up the transition times of the signal. This fix requires the placement of a buffer or buffers somewhere within the routing path of the signal.
In integrated circuit processes that use chemical mechanical polishing (CMP) for planarization, it is necessary to have a fairly even distribution of elements at each layer in the process where CMP is used. Often designers must place large areas of active area, polysilicon, or metal in the large unused areas of an integrated circuit to meet these CMP requirements.
As integrated circuit operating frequencies increase, radiated emissions from the circuit become an increasing problem. When large numbers of devices simultaneously switch in a circuit, the high frequency components of the power supply noise causes radiated emissions that must be suppressed to meet FCC rules. This suppression is often accomplished by adding bypass capacitors to the power supplies.
There is a need for a method of automatically adding transistors to the unused areas of an integrated circuit in a default configuration of adding bypass capacitance to the power supplies. This transistor array must be modifiable to form signal buffers, charge dissipation paths, or other functional circuits as needed.